Computing devices, particularly those found in various automotive, industrial, aerospace and other commercial settings, commonly represent operating modes or other information with sequences of binary digits or “bits” called “data values”. A conventional Karnaugh map, for example, is one technique for generating data values for a given number (“n”) bits. Conventional Karnaugh mapping techniques can be used to identify up to 2n data values from the n bits. The resulting values can be stored in memory and/or exchanged with other computing modules to represent operating states or other appropriate information.
As digital data is stored, processed, consumed and/or shared between modules, bit errors can occur due to environmental factors, hardware faults and other causes. To ensure that data values are reliable, computing systems frequently incorporate error checking techniques such as parity checks, cyclic redundancy checks (CRCs) and/or the like. Conventionally, a program module preparing a data message computes a digital verification code based upon the contents of the message using a particular algorithm. The resulting verification code can then be appended to the message during transmission. The receiving module verifies the code using the same algorithm as the transmitting module to ensure that the contents of the message did not change during transmission; that is, by comparing a code computed prior to transmission with a code computed according to the same algorithm after transmission, the contents of the message can be verified to ensure that no bit errors occurred during transmission. Examples of well-known algorithms for computing reliable verification codes include the so-called CRC32 and MD4 algorithms, among others. While error checking routines are highly reliable, they do exhibit several disadvantages in terms of bandwidth and computing resources. Particularly in the vehicle setting, where computing resources and communications bandwidth are limited, the additional space and time required to transmit verification codes can be undesirable.
It is therefore desirable to formulate a data representation scheme that is capable of efficiently representing data without sacrificing robustness or accuracy. Moreover, it is desirable to create a technique for generating data values for such schemes. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.